1. Field of the Invention
The present invention relates to a semiconductor structure. More particularly, the present invention relates to a triple well structure in a semiconductor substrate.
2. Description of the Related Art
Conventional DRAM process commonly utilizes a twin well structure. The twin well includes a P-well, which is often used for forming a memory region and an N-type MOS, and an N-well, which is used for forming a P-type MOS. However, in an embedded DRAM, a memory region and a logical region are incorporated in the same wafer. Since the memory region and the logical region are supplied with different back bias, in order to prevent bias interference between the logical region and the memory region, a third well must be formed to isolate these two regions from each other. Therefore, it is desired to form the third well, such as a deep well, in the substrate to isolate the logical region and the memory region.
FIG. 1 is schematic, cross-sectional view showing a conventional embedded DRAM memory region having a triple well therein.
Reference is made to FIG. 1, which shows a variety of devices formed on the P-type substrate 200. The active devices of FIG. 1 are described as follows. A transistor 202 is located on the P-type substrate 200. The transistor 202 includes an N-type gate 204, an N-type source 206, and an N-type drain 208. The N-type gate 204 is located on the P-type substrate 200. The N-type source 206 and the N-type drain 208 are in the P-type substrate 200 on different sides of the N-type gate 204. The N-type drain 208 and a capacitor 215 are electrically coupled.
A P-type field 220 is located in the P-type substrate 200 under the transistor 202. An isolation layer 230 and an isolation layer 235 are formed over the first conductive type substrate 200 to isolate active devices from each other. The isolation layer 230 covers an isolation structure 222 and the transistor 202. The isolation layer 235 covers the capacitor 215 and the isolation layer 230. A contact opening 210 is formed in the isolation layer 230 and the isolation layer 235 to expose the N-type source 206. The contact opening 210 is formed for the formation of a bit line (not shown) by the subsequent process.
The isolation devices of FIG. 1 are described as follows. The isolation structure 222 encircles the transistor 202. An isolation N-well 224 is formed under the isolation structure 222 and in contact with the isolation structure 222. A deep N-well 226 underlies the P-type field 220. The isolation N-well 224 is perpendicular to the deep N-well 226. A bottom portion of the isolation N-well 224 overlaps with a side portion of the deep N-well 226. The N-type isolation well 224 and the deep N-well 226 together surround a portion of the P-type substrate 200, which is employed as a P-well 228. The isolation N-well 224, the P-well 228, and the deep N-well 226 together form a triple well structure.
An N-plug 245 is formed in the P-type substrate 200 under the N-type source 206 and in contact with the N-type source 206. The N-plug 245 is used to enlarge and deepen the range of the N-doped region with the N-source, which reduces the current leakage from the bit line to the P-type regions, such as the P-type field 220 or the P-well 228, that near the N-type source 206.
However, the N-plug 245 and the deep N-well 226 are close to each other, and this, in turn, increases the punchthrough effect between the N-plug 245 and the deep N-well 226. In order to decrease the punchthrough effect, P-type ion concentration of the P-type regions near the N-type plug 245 and the deep N-well 226 must be increased.
Unfortunately, as P-type ion concentration of P-type regions near the N-plug 245 and the deep N-well 226 increases, junction leakage between the N-plug 245 and neighboring P-type regions increases correspondingly. Thus, in contrast, in order to prevent junction leakage, it is necessary to reduce the concentration of the neighboring P-type regions. So, in practice, it is difficult to decide whether or not to increase or decrease the concentration of the P-type regions, such as the P-type field 220.